Recently, along with the increasing integration of semiconductor devices, circuit patterns of transistors that comprise the semiconductor devices have been increasingly miniaturized. In response to thinning of wiring lines resulting from the miniaturization, there is a demand for techniques to improve the dimensional accuracy and positional accuracy of the circuit patterns. The field of semiconductor memories is no exception to such circumstances.
Semiconductor memories such as a DRAM, SRAM and flash memory that have been heretofore known and put on the market use a MOSFET as a memory cell. For such semiconductor memories, an improvement in dimensional accuracy at a rate higher than the rate of the miniaturization of the circuit patterns is demanded. Thus, a heavy burden is imposed on a photolithographic technique for forming micro circuit patterns, which is one of the factors of the rise in manufacturing costs.
A resistance change memory is drawing attention as a succeeding candidate memory to overcome the above-mentioned problem.
The resistance change memory is characterized in that an electric pulse is applied to change the resistance of a resistance change film and in that data is stored in the resistance change film in a nonvolatile manner. However, the resistance change memory is also limited in fact in miniaturization from the perspective of processing technologies. Therefore, from now on, there is a need for a technique to enhance integration without depending on miniaturization.
One of the techniques for realizing integration instead of miniaturization is to comprise a three-dimensional memory cell array. However, the three-dimensional memory cell array increases manufacturing costs due to an increase in the number of photo engraving processes (PEP). Moreover, due to an increase in the number of memory cell arrays to be stacked, the characteristics of the memory cell arrays are varied by the difference of process histories.
Accordingly, one technique for realizing integration instead of the miniaturization and three-dimensional configuration is to comprise a multi-level technique that stores three or more values in one memory cell. There are reported examples of applying the multi-level technique to the resistance change memory.
The resistance change memory can have a multi-level system when the resistance change film (memory cell) is capable of storing three or more resistances (three or more values). However, in this case, the resistance change film cannot have a great resistance variation, so that a sufficient margin is not allowed for the three or more resistances. As a result, high reliability is not ensured.
The resistance change memory can also have a multi-level configuration when resistance change films capable of storing, for example, two kinds of resistances (two values) are connected in series or parallel and each of the resistance change films has different two kinds of resistances. However, when the resistance change films are connected in series, such electrical characteristics are shown that a rate is determined by the resistance change film having the highest resistance. When the resistance change films are connected in parallel, such electrical characteristics are shown that a rate is determined by the resistance change film having the lowest resistance. Thus, it is difficult to control writing/erasing.